EngineHall works with KiCad

EngineHall reads a KiCad 9 or 10 project from its files, builds every net from the wire geometry, and checks the schematic, the parts, the board and declared simulations. KiCad's own ERC and DRC run through kicad-cli when it is installed. The kicad-designer skill teaches an AI agent to write and verify KiCad projects.

Download the skill Install EngineHall

What a review reads

The engine is plain Python and parses KiCad's S-expression files itself. It needs neither KiCad nor pcbnew to run, and it never writes into the project.

The .kicad_pro and the whole .kicad_sch hierarchy. Nets come from wires, junctions, labels, sheet pins and power symbols, following connection rules measured against kicad-cli's own netlist export.
The .kicad_pcb: footprints, pads, tracks, vias, the Edge.Cuts outline, silkscreen and courtyards, in the net formats of KiCad 9 and KiCad 10.
pcba-requirements.toml, if present: rail voltages, derating limits, board assembly, connector pinouts and SPICE testbenches.
Component data in JSON: supply ranges, absolute maximums, logic levels and the connections a part requires.
With an STM32 on the sheets and a CubeMX .ioc in the project, the schematic, CubeMX and firmware pin rules run as they do for Altium.

Run it

enginehall doctor --no-ping
enginehall inspect path/to/project
enginehall review path/to/project
enginehall review path/to/project --format sarif > review.sarif
enginehall kicad netlist path/to/project

Exit status 0 means nothing at or above the chosen severity threshold (--fail-on), 1 that there is, 2 that the review could not run. Findings below the threshold still appear in the report. Discovery finds the .kicad_pro; choose one with --kicad-project where there are several. Text, Markdown, JSON and SARIF reports carry each rule's status, so an editor or a code-scanning view opens the sheet, the reference, the pin or the board item a finding names.

Findings, baselines and CI

What it checks

Every rule below ends with a status in the report: passed, failed, info, not checked with the reason, or not applicable. A rule that judged nothing is not checked, never passed.

Schematic and connectivity

ERC finds what KiCad's rules know. These add the mistakes a reviewer looks for by hand.

kicad.erc.violation: Every violation KiCad's ERC reports; library-table messages as info. Needs kicad-cli.
kicad.netlist.parity: The engine's connectivity compared with KiCad's own netlist export. Needs kicad-cli.
kicad.power.rail_without_source: A net with power inputs and no power output or PWR_FLAG.
kicad.power.pin_without_dc_path: An IC power pin that reaches no rail through wires, resistors of at most 1 ohm, inductors, ferrites, fuses or jumpers: only through a capacitor, or not at all.
kicad.power.decoupling_missing: An IC supply net with no capacitor to ground anywhere.
kicad.part.shorted: A two-pin part with both pins on one net. Net ties, jumpers and DNP parts are excepted.
kicad.pin.input_floating: An input pin connected to nothing and without a no-connect flag.
kicad.net.pull_up_missing: An I2C net or an open-drain pin without a resistor to a supply.
kicad.label.global_single_sheet: A global label used on one sheet only (info).
kicad.label.single_connection: A label whose net reaches at most one pin.
kicad.net.name_hygiene: VBUS without a USB connector; a power rail with no voltage in its name (info).

Parts and project requirements

Judged against component data and pcba-requirements.toml. A part without data or a rail of unknown voltage is listed as not judged.

kicad.component.supply_range: Each supply pin's rail inside the part's operating range and absolute maximum; ground pins on ground.
kicad.component.capacitor_derating: The voltage across a capacitor against its rating and the class limit: ceramic 50 %, electrolytic 80 %, tantalum 50 %, film 70 % by default.
kicad.component.resistor_power: The power in a resistor between two rails against 50 % of its rating.
kicad.component.logic_level: Driver output levels against receiver thresholds and input limits on one net; a pull-up above an input's rating.
kicad.component.required_connection: What the component data requires of a pin: a capacitor to ground and its value, not floating, a pull-up or pull-down.
kicad.connector.pin_assignment: Each connector pin carries the signal the declared interface names.

Board and Newmatik house DFM

The house values come from the same module the Altium drive uses; finding titles carry the house id, such as NM-FID-001. Values marked proposed stay proposals.

kicad.drc.violation: Every violation and unconnected item KiCad's DRC reports. Needs kicad-cli.
kicad.drc.schematic_parity: Board and schematic out of step, from KiCad's parity check. Needs kicad-cli.
kicad.dfm.fiducials: NM-FID-001 to 006: three fiducials per SMD side, 1.0 mm round copper, 3.0 mm mask opening, no paste, no net, 3 mm from the edge, forming a real triangle.
kicad.dfm.track_angle: NM-ROUTE-001: tracks at 0, 45 or 90 degrees.
kicad.dfm.via_in_pad: NM-VIA-001: no via in or touching a pad.
kicad.dfm.via_spacing: NM-VIA-002: same-net vias at least 2 mm apart (proposed).
kicad.dfm.model_missing: NM-3D-001: a STEP model for every footprint, and the file exists.
kicad.dfm.silkscreen_outside: NM-SILK-001: no silkscreen beyond the board outline. Text extents are estimated, so text findings are heuristic.
kicad.dfm.barcode_field: NM-BC-001: a square silkscreen field marked BC, at least 5 mm, 7 mm preferred.
kicad.dfm.bottom_side_smd: No SMD part on the bottom of a board declared single-sided.
kicad.dfm.smd_edge_clearance: SMD copper at least the declared distance from the board edge.
kicad.dfm.test_point_coverage: Nets with two or more pads and no test-point footprint.
kicad.dfm.courtyard_overlap: The courtyards of two parts on one side overlap, compared as convex hulls.

Simulation

Declared ngspice testbenches with a pass range, run when ngspice is installed.

simulation.spice.testbench: A declared testbench whose measured value is outside its pass or warn range. Needs ngspice.

KiCad's own checks, when KiCad is installed

kicad-cli and ngspice are optional. The review uses them when it finds them and says so when it does not.

ERC and DRC through kicad-cli: With kicad-cli on the machine, the review runs KiCad's ERC, its DRC with schematic parity, and the netlist export. Their findings carry the detector external. kicad-cli works on a temporary copy, because it writes a .kicad_prl next to the project file it opens.
A second netlist: kicad.netlist.parity compares the nets the engine built with KiCad's own export, so a mistake in the reader becomes a finding instead of a wrong answer.
ngspice testbenches: Declare a deck and its pass range, and the review runs it and compares the measured value. Decks that start programs, write files or include files outside the project are refused; ngspice runs with -n in an empty temporary folder, with a timeout.
Missing means not checked: Without kicad-cli or ngspice, their rules are reported as not checked with the reason, never as passed. enginehall doctor shows what this machine has.

What the files cannot say

Some promises are not in the schematic: the rail voltages, how far a capacitor may be derated, which connector pin carries which signal, whether the board is assembled on one side. Put them in pcba-requirements.toml next to the project. A malformed file stops the review with exit 2, because a promise the review silently ignored would make its result worthless.

A voltage read from a net name such as +3V3 makes a finding heuristic; a declared rail makes it deterministic. Component data uses the same JSON schema as the generic examples the engine ships; real parts go into a project file.

pcba-requirements.toml

version = 1

[rails."+3V3"]
voltage = 3.3
tolerance = 0.05

[board]
assembly = "single-sided"
smd_edge_clearance_mm = 5.0

[[connectors]]
ref = "J2"
interface = "debug"
pins = { "1" = "+3V3", "2" = "SWDIO", "3" = "SWCLK", "4" = "GND" }

[[simulations]]
name = "sense divider"
netlist = "sim/divider.cir"
measure = "vout"
pass = [1.60, 1.70]

In an EngineHall project

The KiCad files stay in your Git repository. The workspace shows them, collects the review of them, and releases them.

Previews in the browser: Connect a GitHub or GitLab repository, and .kicad_sch and .kicad_pcb files open in the browser at any branch or commit, next to PDFs, STEP models and source code.
Check runs per commit: enginehall review --publish, run on your machine or in your CI job, sends the report of a commit to the project: findings, locations and coverage, never the design files.
Design reviews: Reviewers comment on a point of a schematic sheet or the board and approve the revision or request changes.
Releases: A release lists its blockers, collects the approval of each organisation, freezes the documentation, and hands the package to Gerbtrace.

See the workspace

The kicad-designer skill

KiCad files are plain text, so an agent can write schematics, libraries and boards directly and prove them with kicad-cli. That makes mistakes cheap to make. The skill makes the agent work the way a careful engineer does.

Wires, not only labels: A sheet where every pin carries a net label is a netlist, not a schematic. The skill draws function blocks wired to each other, power symbols for rails and junctions at tees, and shows the first sheet before it generates the rest.
Connectivity proven from the file: After every generation run the agent exports KiCad's netlist, compares it net by net with the intended one, then runs enginehall review. ERC alone misses a wire that shorts two nets and a tee drawn without a junction.
Pins from the datasheet: Every non-passive symbol is checked against the part's pin table, and an alternate part against the same pinout.
Coverage, not sign-off: The design lives in one script or data file and is regenerated, never hand-edited. The agent reports what ERC, DRC and the review covered, and quotes the rules that were not checked, with their reasons.

Set it up

Step 1
Install EngineHall
Install the engine as the install page describes. KiCad 9 or 10 and ngspice are optional; enginehall doctor --no-ping shows whether it finds them.
Step 2
Add the skill
Download kicad-designer.zip from this page and add it as a skill: upload it in Claude, or unpack it into your agent's skills folder.
Step 3
Review the project
Run enginehall review on the folder with the .kicad_pro, or ask your agent to. Read the rule statuses before you trust a clean result.

The design stays where it is

The review runs on your machine or in your CI. Nothing about the design is sent to enginehall.com unless you publish a report, and then only its findings, locations and coverage. Your agent's provider sees what you share with the agent.

What stays with you

Gerber, drill, pick-and-place and BOM files belong to Gerbtrace. The review reads KiCad source files, never fabrication outputs.
Buses and bus aliases are not resolved yet. A note says so, and the netlist comparison shows the affected nets when kicad-cli runs.
Net classes, custom DRC rules and zone fills are KiCad's. They reach the review only through kicad.drc.violation.
The component data the engine ships is generic and invented. Real parts go into your project's component file, with the datasheet page.
A clean review covers the rules marked passed, with their unchecked items, and nothing else. It is an assisted review, not a sign-off.

KiCad is named here to describe compatibility. EngineHall is not affiliated with or endorsed by the KiCad project.